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DTSTAMP:20230124T171522Z
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DTSTART;TZID=America/Chicago:20221117T083000
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UID:submissions.supercomputing.org_SC22_sess275_rpost196@linklings.com
SUMMARY:Leveraging Stencil Computation Performance with Temporal Blocking 
 Using Large Cache Capacity on AMD EPYC 7003 Processors with AMD 3D V-Cache
  Technology
DESCRIPTION:Posters, Research Posters\n\nLeveraging Stencil Computation Pe
 rformance with Temporal Blocking Using Large Cache Capacity on AMD EPYC 70
 03 Processors with AMD 3D V-Cache Technology\n\nQu, Ltaief, Keyes\n\nIn st
 ructured grid finite-difference, finite-volume, and finite-element discret
 izations of partial differential equation conservation laws, regular stenc
 il computations constitute the main core kernel in many temporally explici
 t approaches for such problems. For various blocking dimensions, the Spati
 al Blocking (SB) approach enables data reuse within multiple cache levels.
 \n\nIntroduced in GIRIH, the Multi-core Wavefront Diamond blocking (MWD) m
 ethod optimizes practically relevant stencil algorithms by combining the c
 oncepts of diamond tiling and multi-core aware wavefront temporal blocking
 , leading to significant increase in data reuse and locality.\n\nWe evalua
 te the performance of MWD on a variety of recent multi-core architectures.
  Among all of them, the new AMD multi-processor, codenamed Milan-X, provid
 es an unprecedented capacity for the Last Level Cache. We show that the Mi
 lan-X hardware design is ideal for the MWD method, and significant perform
 ance gain can be achieved relative to its predecessors Milan and Rome.\n\n
 Registration Category: Tech Program Reg Pass, Exhibits Reg Pass
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