The International Conference for High Performance Computing, Networking, Storage, and Analysis
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Workshop: HiPar22: 3rd Workshop on Hierarchical Parallelism for Exascale Computing
Authors: Ari Rasch, Richard Schulze, and Sergei Gorlatch (University of Muenster)
Abstract: The optimization processes of modern compilers are often guided by performance experts who express optimization via so-called scheduling languages. We present our work-in-progress results toward a novel compiler whose scheduling language is based on the approach of Multi-Dimensional Homomorphisms (MDH). We argue that our MDH-based scheduling language enables a structured, hierarchical optimization process, by offering scheduling commands that systematically de- and re-compose computations to/from the memory and core hierarchies of state-of-the-art architectures (GPUs, multi-core CPUs, etc). Thereby, a performance expert expresses hierarchical code optimizations in a concise and structured way, contributing to a simplified code optimization process. Our first experiments on NVIDIA GPU and Intel CPU show that our scheduling language is capable of expressing as hierarchical code optimizations the optimization decisions of the popular deep learning compiler TVM. Our experiments also confirm that via auto-tuning, we are able to achieve better performance than TVM on both architectures.
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