The International Conference for High Performance Computing, Networking, Storage, and Analysis
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Workshop: Third International Symposium on Checkpointing for Supercomputing (SuperCheck-SC22)
Authors: Kurt Keville (Massachusetts Institute of Technology (MIT)) and Po Hao Chen (Boston University)
Abstract: We present nascent work that introduces a path forward for leveraging CXL 2.0 and 3.0 subprotocols, notably the CXL.cache and CXL.mem subprotocols, in a novel fashion. We intend to demonstrate CXL Type 1 and Type 2 device functionality in order to make a strong case for more and larger cache levels. This will not only create a novel memory hierarchy for us to accelerate precomputed (speculated) memory paths but will effectively operate as a live checkpoint and snapshot option since we are moving many traditional RAM operations onto redefined non-volatile media, initially CXL-enabled NVMe drives.